The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2002
Filed:
Jul. 21, 2000
Shigeki Aoki, Shiojiri, JP;
Haruo Kamijo, Nagano, JP;
Seiko Epson Corporation, Tokyo, JP;
Abstract
A semiconductor integrated circuit has a reset signal generation circuit ( ) that generates a reset signal ( ) having a reset period based on a power-on reset signal ( ), and a latch circuit ( ) having an initialization circuit ( ) that initializes a latch output ( ) based on the reset signal ( ). The reset signal generation circuit ( ) has a delay circuit ( ) that can variably set a pulse width corresponding to the reset period of the reset signal ( ). An output line of the delay circuit ( ) is connected to a first pad terminal ( ). An output line of the initialization circuit ( ) is connected to a second pad terminal ( ). When the semiconductor integrated circuit is verified, the first and second pad terminals ( ) are brought in contact with a probe ( ). During this verification process, according to input/output loads of a tester that is connected to the first pad terminal ( ), the pulse width of the reset signal ( ) is set wider than that during the normal use when the pad terminals are not contacted with a probe.