The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2002

Filed:

Nov. 13, 2000
Applicant:
Inventors:

Michimasa Tsuzaki, Neyagawa, JP;

Nobuteru Maekawa, Katano, JP;

Narimasa Iwamoto, Nabari, JP;

Junji Imai, Amagasaki, JP;

Hiroaki Okada, Nara, JP;

Teruaki Komatsu, Hikone, JP;

Shinya Murase, Hikone, JP;

Hiroyuki Inoue, Hikone, JP;

Masayuki Sagawa, Hikone, JP;

Yuri Sakai, Monbetsu, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/334 ;
U.S. Cl.
CPC ...
H01L 2/334 ;
Abstract

A thermoelectric module is capable of successfully reducing the heat stress for increased reliability. The module includes a plurality of thermoelectric chips of P-type and N-type arranged in a matrix between sets of first and second contacts to form a series electrical circuit. The chips are arranged to give at least three chip arrays each having a limited number of the chips. A first carrier is provided on one side of the chips to carry the first contacts and to include first bridges each integrally joining two adjacent first contacts to define first discrete couples for electrical connection of the chips in each chip array. The first carrier further includes at least two inter-array bridges which are solely responsible for electrical interconnection between the adjacent chip arrays. On the opposite side of the chips, there are formed a plurality of second bridges each integrally joining the two adjacent second contacts to give second discrete couples for electrical connection of the two adjacent chips in each of the chip arrays. Thus, the inter-array bridges are formed only on one side of the chips for interconnection of the first contacts between the adjacent chip arrays. Therefore, the heat stress applied to the end of the chip array where the two adjacent chip arrays are interconnected can be well relieved on the side of the second contacts in which the second discrete couples are kept totally isolated from each other.


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