The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2002

Filed:

Mar. 28, 2000
Applicant:
Inventors:

Hitoshi Iwata, Aichi, JP;

Makoto Murate, Aichi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/100 ;
U.S. Cl.
CPC ...
H01L 2/100 ;
Abstract

A method for anodizing silicon substrate includes forming an n-type silicon embedded layer ( ) made of n-type silicon on a predetermined area of a first surface of the p-type single crystal silicon substrate ( ). N-type silicon layers ( ) are formed on the upper surface of the p-type single crystal silicon substrate ( ) and on the n-type silicon embedded layer ( ). Silicon diffusion layers ( ) containing high-concentration p-type impurities are formed on predetermined areas of the n-type silicon layers ( ) to contact the n-type silicon embedded layer ( ). An electrode layer ( ) is formed on the lower surface of the p-type silicon substrate ( ). The anode of a DC power source ( ) is connected to the electrode layer ( ), and the cathode is connected to a counter electrode ( ), which is opposed to the p-type silicon substrate ( ). A current is intensively applied to an area corresponding to an opening ( ) of the n-type silicon layer ( ) in a direction from the lower surface to the upper surface of the p-type single crystal silicon substrate ( ), which makes the area porous.


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