The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 04, 2002

Filed:

Sep. 05, 2000
Applicant:
Inventors:

Charles C. Haluzak, Corvallis, OR (US);

Colby Van Vooren, Corvallis, OR (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B41J 2/05 ;
U.S. Cl.
CPC ...
B41J 2/05 ;
Abstract

Described herein is a monolithic printhead formed using integrated circuit techniques. Thin film layers, including ink ejection elements, are formed on a top surface of a silicon substrate. The various layers are etched to provide conductive leads to the ink ejection elements. A trench is etched in the bottom surface of the substrate, leaving a thin silicon shelf or membrane. Ink feed holes (individual holes or a second trench) are formed in the silicon shelf or membrane, and ink feed holes are formed in the thin film layers, so that ink can flow into the trench and into each ink ejection chamber through the ink feed holes. The ink ejection elements reside over the silicon shelf or membrane so that the shelf or membrane provides mechanical stability, prevents thin film layer buckling, and improves the heat transfer between the ink ejection elements and the substrate. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate. An orifice layer is formed on the top surface of the thin film layers to define the nozzles and ink ejection chambers.


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