The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2002

Filed:

Feb. 18, 2000
Applicant:
Inventors:

Adam Stuart Block, Fort Collins, CO (US);

Jeffrey P Witte, Ft Collins, CO (US);

Don D Josephson, Ft Collins, CO (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ; H01L 2/503 ; H03K 1/900 ;
U.S. Cl.
CPC ...
G06F 1/750 ; H01L 2/503 ; H03K 1/900 ;
Abstract

A method and system for managing metal resources in the physical design of integrated circuits is presented. Percent metal usage is allocated for intra-block routing use by each functional block. Power and clock grids are established. Block designers coordinate the locations of signal ports of the blocks so as to avoid blocking any inter-block signals, areas of metal are then reserved for ports and intra-block signals. The inter-block signals are then pre-routed, avoiding the power grid, clock grid, and reserved intra-block routing metal. If any problem nets emerge from the pre-routing, better port locations and sub-block placement within the respective blocks are determined and the process is repeated.


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