Reduced-pin integrated circuit i/o test

Abstract

The present invention provides a method and device for reduced-pin integrated circuit I/O testing. In this regard, the present invention provides for the testing of an integrated circuit or chip in a manner which is independent of the number of test pins present on the testing device. The method and device of the present invention are realized through an integrated circuit having two test ports: a scannable I/O test port and a Forcing-Measuring test port, and a plurality of switches. The scannable I/O test port is employed for the input and output of, among other things, scannable shift-register latch data which affects the states of the plurality of switches in the integrated circuit. The Forcing-Measuring test port is employed for, among other things, forcing or measuring voltages and currents associated with the I/O circuits under test through the switches to the circuits under test. The methods of the present invention are embodied in a plurality of test configurations including: an I/O Short-Circuit test configuration which verifies that each I/O is not short-circuited to a supply voltage or to ground; an I/O Negative and Positive Leakage test configuration; a Pull-Up and Pull-Down Resistor test configuration; Differential I/O test configuration; a Package test configuration; an I/O Driver Least Positive Up Level (LPUL) and Most Positive Down Level (MPDL) test configuration; a single-ended I/O receiver LPUL and MPDL test configuration; a differential I/O receiver LPUL and MPDL test configuration; and Differential I/O Terminator Resistor Test configuration.