The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2002

Filed:

Jun. 26, 2000
Applicant:
Inventors:

Brian James Knight, Cambridge, GB;

Fash Nowashdi, Luton, GB;

Assignee:

Virata Ltd., Cambridge, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/200 ;
U.S. Cl.
CPC ...
G06F 1/200 ;
Abstract

A method and apparatus for controlling memory access in a system where at least a first and a second processor each share a common memory. The first processor has a write buffer, in which it stores words prior to writing them in the common memory, and a cache for receiving words from the common memory. The common memory is mapped twice into the address space of the first processor so that, in a first mapping, the first processor accesses the common memory directly and in a second mapping, the cache is enabled. The common memory can therefore be directly accessed with the first processor and the second processor when they share data that is read from or written into the common memory. The cache is accessed with the first processor in the second mapping for reading and writing data local to the first processor. Information written into the write buffer is tagged and the tagged information is flushed into the shared memory before the shared memory can be accessed by the second processor.


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