Self test of an electronic device

Abstract

The present invention provides for improved loopback testing of an electronic communications device. The electronic communications device ( ) includes a transmit serializer ( ), a transmit output buffer ( ), a first phase interpolator ( ), a phase locked loop ( ), a second phase interpolator ( ), a receive deserializer ( ), a receive input buffer ( ), and phase adjust logic ( ). The PLL ( ) generates a timing signal in accordance with a reference clock signal ( ). In one mode of operation, the transmit serializer ( ) transmits data for output through the transmit output buffer ( ) in accordance with the timing signal generated by the PLL ( ). In another mode of operation, the phase interpolator ( ) accepts as input the timing signal generated by the PLL ( ). The phase interpolator ( ) then generates an altered timing signal which the transmit serializer ( ) uses to transmits data for output through the transmit output buffer ( ) asynchronously from the timing signal of the receive deserializer ( ).