Delay locked loop of a ddr sdram

Abstract

A delay locked loop is disclosed which is capable of operating at both of a rising edge and a falling edge of a clock. The delay locked loop includes: a first differential amplifier receiving a clock at a positive input and an inverted clock at a negative input for buffering; a second differential amplifier receiving the clock at a negative input and the inverted clock at a positive input for buffering; a delay circuit receiving the outputs of the first and second differential amplifiers for delaying in time the clock by a skew to be compensated; a measurement delay line for adjusting time delay of the output of the delay circuit in a first direction; a phase comparator receiving the outputs of the measurement delay line and the first differential amplifier for applying the clock by the adjusted time delay; a variation delay line receiving the output of the phase comparator and the output of the first differential amplifier for adjusting the time delay in a second direction; a duplicate delay line receiving the output of the variation delay line and the output of the second differential amplifier for delaying in time the clock as adjusted by the measurement delay line; and an output buffer receiving the outputs of the variation delay line and the duplicate delay line to output a delay locked loop clock signal.