The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2002

Filed:

May. 30, 1997
Applicant:
Inventor:

Kiyokazu Ishige, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/7108 ;
U.S. Cl.
CPC ...
H01L 2/7108 ;
Abstract

There is provided a semiconductor memory device including a semiconductor substrate, a floating gate type transistor formed on the semiconductor substrate, acting as a memory cell of the semiconductor memory device, and a charge pump circuit formed on the semiconductor substrate. The transistor includes (a) a first gate insulating film formed on the semiconductor substrate, (b) a floating gate electrode formed on the first gate insulating film, (c) a second gate insulating film formed on the floating gate electrode, and (d) a control gate electrode formed on the second gate insulating film. The charge pump circuit includes (a) a plurality of diode devices formed on a third insulating layer formed on the semiconductor substrate, and electrically connected with each other in series, and (b) a plurality of capacitors each of which is electrically connected to a terminal of each of the diode devices. The above mentioned semiconductor memory device significantly reduces a parasitic capacity to thereby enhance a step-up efficiency. Thus, it is possible to reduce power consumption in a charge pump circuit and further reduce a total area required for a semiconductor memory device.


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