The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 28, 2002

Filed:

Sep. 16, 1999
Applicant:
Inventors:

Thomas Craig Esry, Orlando, FL (US);

Nace Layadi, Orlando, FL (US);

Sylvia Marci Luque, Orlando, FL (US);

Simon John Molloy, Orlando, FL (US);

Mario Pita, Winter Springs, FL (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/13065 ;
U.S. Cl.
CPC ...
H01L 2/13065 ;
Abstract

A process for forming a patterned film structure within a semiconductor device. The process sequentially forms a pattern within a hardmask film and than within a semiconductor or other film formed beneath the hardmask film. The etch bias of both isolated and nested features formed within the films, is substantially the same with respect to a masking film formed over the hardmask film. The process includes a hardmask film etching sequence including an argon treatment step and a hardmask film etching step which is resistant to localized etching effects and includes O and C F as etchant gasses.


Find Patent Forward Citations

Esry, Thomas. (2002). Process for improving line width variations between tightly spaced and isolated features in integrated circuits (U.S. Patent No. 6395639). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6395639

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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