Skew-independent memory architecture

Abstract

A word line block, a data block and at least one memory cell form a memory architecture and impose no special timing requirements to handle the synchronization of the outputs of the word line block with the data block. Further, the word line block contains a transmitting transistor and the data block contains a functionally similar transmitting transistor. These transmitting transistors responsive to a write enable signal and a clock signal synchronize a selection signal supplied to the memory cell when data is also supplied to the memory cell. Furthermore, a place in route tool can automatically place and route the word line block, the data block and the at least one memory cell based on chip requirements. Also, with the clock signal proximate the output of the word line block and data block, the place and route tool is able to automatically place and route the blocks and the at least one memory cell to compensate for any calculated interconnection delays. Moreover, since the word line block, the data block, and the at least one memory cell are separate blocks, flexibility is provided in the placement of the blocks as each block requires a reduced amount of layout space as compared to all three blocks together. Also provided is a process using synthesis method for creating a digital electronic circuit with the memory architecture including the word line block, the data block, and the at least one memory cell.