The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2002

Filed:

May. 26, 1999
Applicant:
Inventors:

Balraj Singh, Morgan Hill, CA (US);

Eric Chesters, Mountain View, CA (US);

Venkat Mattela, San Jose, CA (US);

Rod G. Fleck, Mountain View, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/516 ;
U.S. Cl.
CPC ...
G06F 1/516 ;
Abstract

A method and an apparatus for reducing the number of instruction transactions in a microprocessor are disclosed. As a method, the number of issued instructions carried by an issued instruction bus in a computer system are reduced by determining if an instruction fetched by a fetch unit matches a cached instruction tag. When the fetched instruction matches the cached instruction tag, an opcode and an associated instruction corresponding to the cached instruction tag are directly injected to an appropriate function unit. The apparatus includes a plurality of tag PC cache memory devices used to store tag PC entries associated with target instructions injected directly to corresponding function units included microprocessors and the like. The injection reduces the number of instructions fetched from the program memory as well as the number of issued instructions carried by an issued instruction bus.


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