Method and apparatus for performing load bypasses in a floating-point unit

Abstract

The present invention provides a method and apparatus for performing load bypasses with data conversion in a floating-point unit. This process of reading instructions and data out of a cache memory component, of decoding the instructions, of performing the a memory-format-to-register format conversion and of writing the converted data to the register file block of a floating-point unit is known as a load operation. A load operation occurs over many cycles. In accordance with the present invention, the number of cycles required to perform a load operation has been shortened, thereby dramatically increasing the overall throughput of the floating-point unit. In accordance with the present invention, the floating-point unit performs a load bypass with conversion, which significantly shortens the load operation. Data received by the floating-point unit must be converted from a memory format into a register format. The bypass component of the floating-point unit partially converts the data, performs special case exponent detection and generates special case flags. The results of the partial conversion process and the special case flags are then bypassed to the multiply accumulate unit of the floating-point unit. The multiply accumulate unit completes the conversion process while it is performing a first part of the arithmetic operation on the partially converted data. By the time the arithmetic operation has been performed on the partially converted data, the final conversion is complete and the exponent value is available. The remainder of the arithmetic operation is then performed by the multiply accumulate unit on the fully converted data.