Pll circuit for digital display apparatus

Abstract

A PLL circuit is provided with a lock/unlock detection circuit which detects the locked or unlocked state of the PLL circuit by comparing the phases of a horizontal synchronizing signal with each other and an internal synchronizing signal generating circuit which outputs the comparison signal as an internal synchronizing signal when the locked state is detected or outputs the horizontal synchronizing signal as an internal synchronizing signal when the unlocked state is detected. Another mode of a PLL circuit is provided with a skew detecting circuit which resets a frequency dividing circuit upon detecting a skew which is deviated from a normal period in an external synchronizing signal, generates a dummy pulse upon detecting that no skew occurs in the external synchronizing signal in the normal period, and generates a reference signal in combination of the dummy pulse with the external synchronizing signal. When the skew detection circuit detects a skew, the circuit also resets a phase comparator circuit. A digital display apparatus having such a PLL circuit prevents disturbance of the image when the PLL circuit is in an unlocked state or a skew occurs.