The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 21, 2002

Filed:

Jul. 07, 2000
Applicant:
Inventor:

Yoshiaki Morishita, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/302 ;
U.S. Cl.
CPC ...
H01L 2/302 ;
Abstract

The present invention provides a semiconductor device comprising a plurality of semiconductor bear chips staked over a substrate, each of the semiconductor bear chips having top and bottom surfaces, each of the top and bottom surfaces of each of the semiconductor bear chips having both plural signal pads and plural chip select pads, wherein the plural chip select pads are aligned at a constant pitch in a first direction, and adjacent two of the plural semiconductor bear chips are displaced by a first distance corresponds to the constant pitch in the first direction.


Find Patent Forward Citations

Morishita, Yoshiaki. (2002). Multi-level stacked semiconductor bear chips with the same electrode pad patterns (U.S. Patent No. 6392292). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6392292

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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