Method for fabricating a capacitor in a semiconductor memory device

Abstract

A method for making a capacitor of a semiconductor memory device capable of providing increased capacitance without degraded resolution, as well as without the removal of any interlayer insulation layers upon formation of a lower electrode for the capacitor, wherein after formation of an access transistor on a semiconductor substrate, a first interlayer insulation layer for planarization of a surface of the semiconductor substrate and a second interlayer insulation layer for formation of the capacitor lower electrode are formed. After formation of an opening for exposing a part of an impurity diffusion region of the access transistor by etching a part of the first and second interlayer insulating layers, a spacer is formed within the opening. Further, after deposition of a conductive layer for the capacitor lower electrode onto a surface of the substrate, a planarization process is carried out until a part of the upper surface of the spacer is exposed. Finally, after removal of the exposed spacer, the dielectric layer and a conductive layer for the upper electrode of the capacitor are formed in sequence. The method does not require any additional insulation layer evaporation process, since the interlayer insulation layer for formation of the reverse storage electrode could be used for formation of a gate contact of a logic region, without removal. Consequently, simplification of fabrication process for a capacitor is achieved.