The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2002
Filed:
Jun. 29, 1999
Jin Keun Oh, Kyoungki-do, KR;
Young Hee Kim, Kyoungki-do, KR;
Hyundai Electronics Industries Co., Ltd., Ichon-shi, KR;
Abstract
A semiconductor memory test circuit and a method for the same to reduce the test time in testing a semiconductor memory. The semiconductor memory test circuit includes: a parallel test circuit for performing a parallel test when inputting a battery backup signal (bbu), a column address signal (cas ), a CAS before RAS signal (cbr), a write enable signal (ew), a power-up bar signal (pwrupb), and a row address signal (ras )); and a test mode circuit which is controlled by a combination of a parallel test signal (pt) and the battery backup signal (bbu) generated from the parallel test circuit, and generates a test time reduction signal (ttrb), whereby the semiconductor memory test circuit compresses one least significant bit indicating a row address of a device in the case of a 4K refresh operation when the test time reduction signal (ttrb) is enabled, and compresses two least significant bits indicating a row address of a device in the case of an 8K refresh operation when the test time reduction signal (ttrb) is enabled.