The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2002
Filed:
Jul. 07, 1999
Atsushi Yoshikawa, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
In an adder apparatus, a first logic circuit performs a NOR operation upon a first bit of an n-bit input signal and a control signal to generate a first signal. A second logic circuit performs an OR operation upon the first bit of the n-bit input signal and the control signal to generate a logic OR signal and performs a NAND operation upon the logic OR signal and a second bit of the n-bit input signal to generate a second signal. Each of third logic circuits performs a NAND operation upon an (i−1)th (i=3, 4, . . . , n) bit of the n-bit input signal and i-th bit of the n-bit input signal to generate a third signal. A carry signal generating circuit receives the first, second and third signals to generate “n” carry signals. A sum generation circuit receives the n-bit input signal, the “n” carry signals and the control signal to generate an (n+1)-bit output signal and includes a fourth logic circuit for performing an exclusive NOR operation upon the first bit of the n-bit input signal and the control signal to generate a first bit of the (n+1)-bit output signal.