Digital clock/data signal recovery method and apparatus

Abstract

For a digital communications receiver, a clock and data signal recovery circuit and method use an all digital delay locked loop timed by an on-chip transmit clock signal. The digital delay locked loop includes a phase detector and loop filter. The phase detector determines, for each data signal rising or falling edge, if the current delay of a reference clock signal leads or lags the data signal edge. The loop filter examines the stream of such lead/lag indications, performs a nonlinear filtering process thereon, and in response increases or decreases the clock signal phase appropriately.