The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2002

Filed:

Sep. 05, 2001
Applicant:
Inventor:

Thomas E. Obremski, South Burlington, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 2/900 ;
U.S. Cl.
CPC ...
G11C 2/900 ;
Abstract

A method for generating a selected subset of memory addresses associated with a semiconductor memory array is disclosed. In an exemplary embodiment of the invention, the method includes configuring an address counter to generate addresses corresponding to locations within the memory array. A mask register is programmed with a series of masking bits, the value of the masking bits determining whether corresponding address bits in the address counter are masked or not masked. Any of the address bits in the address counter corresponding to a masked bit are masked from a counting operation performed by the address counter, thereby causing the address counter to generate the selected subset of memory addresses.


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Obremski, Thomas. (2002). Method and apparatus for ram built-in self test (bist) address generation using bit-wise masking of counters (U.S. Patent No. 6388930). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6388930

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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