The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2002
Filed:
Sep. 30, 1999
Richard A. Ward, Santa Anna, CA (US);
Mark R. Tennyson, Irvine, CA (US);
Anil Mankar, Mission Viejo, CA (US);
Conexant Systems, Inc., Newport Beach, CA (US);
Abstract
An integrated circuit comprising a relatively simple high voltage tolerant output circuit that may be placed in a high impedance state (i.e., tri-stated) when the voltage at a corresponding signal connection point reaches a predetermined voltage reflecting a logic high level. In one embodiment of the invention, the output circuit is responsive to assertion of a control signal to selectively enter a high impedance state. The control signal is asserted by a control circuit following the detection of a logic high signal of a predetermined duration at the external signal connection point. The predetermined duration may correspond to transmission line delays of a signal line driven by the output circuit. For example, the delay in placing the output circuit in a high impedance state may correspond to the length of time needed to allow transmission line reflections to dissipate to an acceptable level. Disabling the output circuit following such a delay severs the potential current path between the supply voltage of the integrated circuit and an external voltage source coupled to the signal line via a pull-up device.