The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2002
Filed:
May. 03, 2000
Akihiko Iwaya, Tokyo, JP;
Toshio Sugano, Kodaira, JP;
Susumu Hatano, Higashimurayama, JP;
Yutaka Kagaya, Higashimurayama, JP;
Masachika Masuda, Tokorozawa, JP;
Other;
Abstract
A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips are mounted on a substrate in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate . Each chip has a plurality of pads which are disposed thereon into an almost linear array substantially along the center line in the direction of short side edges, which pads include addressing pads that are located on the side of central part on a specified plane of the substrate , and control-use pads of control signals that are also placed on the center side of the substrate . The pad array also includes input/output pads that are disposed so that these are on the peripheral side on the surface of substrate