The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 14, 2002
Filed:
Dec. 17, 1999
Claude L. Bertin, South Burlington, VT (US);
Erik L. Hedberg, Essex Junction, VT (US);
Russell J. Houghton, Essex Junction, VT (US);
Max G. Levy, Essex Junction, VT (US);
Rick L. Mohler, Williston, VT (US);
William R. Tonti, Essex Junction, VT (US);
Wayne M. Trickle, Fairfax, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. A second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a first dielectric material lining the interior surface and a second dielectric material filling the lined trench. The second logic element further comprises a dielectric layer formed over a portion of the first layer and contacting the first dielectric material lining the trench at a merge location; and an electrode extending over a portion of both the dielectric layer and the filled trench. The second logic element is configured so that a predetermined voltage or higher applied between the electrode and the first layer causes a breakdown near the merge location.