The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 14, 2002

Filed:

Dec. 30, 1999
Applicant:
Inventors:

Pierre J. Verlinden, Palo Alto, CA (US);

Akira Terao, Cupertino, CA (US);

Haruo Nakamura, Wako, JP;

Norio Komura, Wako, JP;

Yasuo Sugimoto, Wako, JP;

Junichi Ohmura, Wako, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/100 ;
U.S. Cl.
CPC ...
H01L 2/100 ;
Abstract

A method of fabricating a back surface point contact silicon solar cell having p-doped regions and n-doped regions on the same side by forming a passivating layer on a surface of the cell having opened windows at the p-doped regions and the n-doped regions, by depositing and patterning a first metal layer on the passivating layer in such a way that the first metal layer comes into contact with the p-doped regions and the n-doped regions, by depositing an insulator layer of polyimide on the first metal layer, by etching and patterning the insulator layer of polyimide in such a way that the insulator layer has opened windows at, at least one of the p-doped regions and the n-doped regions, by curing the insulator layer of polyimide by heating at temperature for a period, by additionally curing the insulator layer of polyimide by heating at a second temperature, which is higher than the first temperature, and by depositing a second metal layer made of metal stack on the insulator layer of polyimide in such a way that the second metal layer comes into contact with the one of the p-doped regions and the n-doped regions. With this, the cell surface to be soldered onto a metallized substrate is well planarized and even to ensure sufficient conductibility, with less voids and less solder fatigue.


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