Synchronous semiconductor integrated circuit device capable of test time reduction

Abstract

A synchronous semiconductor memory device in a test mode of operation receives an external clock signal and is controlled by an internal clock adjustment circuit producing an internal clock signal of high frequency to provide write and read operations. A clock cycle converter circuit included in the internal clock adjustment circuit included in the internal clock adjustment circuit produces the internal clock signal by performing a hierarchical exclusive-OR operation on a specific pair of two of eight clock signals successively delayed in phase with respect to the external clock signal.