The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 07, 2002

Filed:

Dec. 28, 2000
Applicant:
Inventors:

Hiroyuki Yamada, Kanagawa, JP;

Kazuo Suto, Tokyo, JP;

Hidehisa Murayama, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/716 ;
U.S. Cl.
CPC ...
H03K 1/716 ;
Abstract

A signal deciding apparatus which can obtain a stable digital signal OUT irrespective of an amplitude and a duty ratio of an input signal IN is provided. The input signal IN is amplified by inverters ( to and ) and outputted as a digital signal OUT. A signal (S ) on the input side of the inverter ( ) is integrated by a time constant which is equal to a data period of the input signal IN by an integrator ( ) and supplied to a differential amplifier ( ). A signal (S ) on the output side of the inverter ( ) is integrated by a large time constant by an integrator ( ), a control voltage VC supplied from a control terminal ( ) is multiplexed to the integrated signal S and a resultant signal is sent to the differential amplifier ( ). An output signal of the differential amplifier ( ) is integrated by a resistor ( ) and a capacitor ( ) and its average level is fed back as a threshold voltage to the input side of the inverter ( ) through a resistor ( ) and multiplexed to the input signal IN. Thus, the digital signal OUT based on the duty ratio of the input signal IN is obtained.


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