Snoopy test access port architecture for electronic circuits including embedded core having test access port with instruction driven wake-up

Abstract

This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. An internal state in the test access port controller, such as bits in a data register, controls the switch state of the programmable switch. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the embedded core circuit under test. The test access port controller can regain control of the test access port and disconnect all of the embedded core circuits when in snoopy states upon detection of a wake-up instruction loaded into a snoopy instruction register during a snoopy state corresponding to an instruction input state. Alternatively, a count of instruction bits more than the most bits for instruction input for any embedded core can trigger the wake-up function.