The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2002
Filed:
Jan. 29, 1999
Francisco A. Cano, Missouri City, TX (US);
Rajib Nag, Missouri City, TX (US);
Robert E. Farrell, Murphy, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A clock generation circuit with a selectable non-overlap time period is described for use on an integrated circuit. A master clock signal M which has a latching edge is formed in response to a reference clock signal fclk. A slave clock signal S which has a driving edge is also formed in response to the reference clock signal. The driving edge of slave clock S is delayed by a non-overlap feedback path so that the driving edge is delayed by the non-overlap time period after the latching edge of master clock M. The value of the non-overlap time period is selected by switching delay circuitry in or out of the non-overlap feedback path on signal line . A control signal STRSTST is set high or low to select the value of the non-overlap time period. A sense circuit or a scan latch also can select the non-overlap time period.