Method and system for destination-sensitive memory control and access in data processing systems

Abstract

A method and system providing a memory controller having a destination-sensitive memory request reordering device. The destination-sensitive memory request reordering device includes a centralized state machine operably connected to one or more memory devices and one or more reorder and bank select engines. The centralized state machine is structured such that control information can be received from at least one of the one or more reorder and bank select engines over the one or more control lines. The centralized state machine is structured such that memory status information can be received from at least one of the one or more reorder and bank select engines over the one or more memory status lines, or such that memory status information can be determined by tracking past memory related activity. Additionally, the centralized state machine is structured to accept memory access requests having associated origin information. The centralized state machine executes the memory access requests based upon the associated origin information and the memory status information. Other embodiments function analogously, with the addition that the centralized state machine incorporates one or more device arbiter and state engines which function as autonomous units generally dedicated to one specific system memory device. The device arbiter and state engines receive identical inputs as discussed for the centralized state machine, except that typically each device arbiter and state engine is dedicated to one particular memory device, and thus generally receives memory status from the memory device with which it is associated via its dedicated memory status line.