The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 30, 2002
Filed:
Apr. 29, 1999
Glenn T Colon-Bonet, Ft Collins, CO (US);
Paul Robert Thayer, Fort Collins, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A Multiply Accumulate unit, which may be an FMAC for IEEE 754 format numbers, finds A*B±C faster if the multiplier is allowed to assume that it's A and B inputs are always positive, so that it never has to provide a complemented output, and if the C input for the accumulation with the product is also assumed to be positive. The sign magnitude notation of the IEEE 754 format is temporarily exchanged for a positive two's complement notation of the assumed positive values. Notice is taken of the actual signs, and when there is a difference to be formed, either because of addition between numbers having opposite signs, or because of a subtraction between numbers having the same sign, one of the numbers need to be negated (complemented) prior to the addition of C and the product AB. That number can always be C, provided that correct compensatory negation is available after the addition. Such negations of C are accomplished by performing a one's complement followed by a carry-in to the subsequent adder. Each of the complemented and the non-complemented C values are readily available. Their production and the selection of one or the other are operations that overlap the execution of the multiply, and are done in a way that does not increase the path delay through the shifter. The accumulated result will typically need to be normalized, after which it may need a final complement operation to adjust its sign, in accordance with the original signs and whether the accumulation was addition or subtraction. The result may be converted back to the IEEE 754 format in due course.