Method and a circuit architecture for testing an integrated circuit comprising a programmable, non-volatile memory

Abstract

A method for testing a programmable, nonvolatile memory including a matrix of memory cells is provided. A plurality of memory cells are programmed. The programmed memory cells are addressed in succession to identify a lowest of threshold voltage levels. The addressing for each memory location includes applying a selection voltage that is lower than the lowest threshold voltage level corresponding to a memory location currently being addressed. The bits are read from the programmed memory cells for the memory location currently being addressed. The reading is repeated while progressively changing the selection voltage supplied to the word line corresponding to the memory location currently being addressed until it is detected that at least one of the bits of the memory location currently being addressed has switched from a first logic level corresponding to a reading of a programmed memory cell to a second logic level corresponding to a reading of a non-programmed memory cell. The low threshold voltage level is compared in the memory location currently being addressed as determined in the reading with a stored value corresponding to the lowest of the low threshold voltages of the memory locations previously addressed.