Method of manufacturing a hybrid integrated circuit comprising a semiconductor element and a piezoelectric filter

Abstract

A method of manufacturing a hybrid integrated circuit comprising a semiconductor element ( ) and a piezoelectric filter ( ), which are situated next to each other and connected to a carrier substrate ( ). The semiconductor element comprises semiconductor regions ( ) which are formed in a silicon layer ( ); the piezoelectric filter comprises an acoustic resonator ( ) which is situated on an acoustic reflector layer ( ), which acoustic resonator comprises a layer of piezoelectric material ( ), a first electrode ( ) situated between the layer of piezoelectric material and the acoustic reflector layer, and a second electrode ( ) which is situated on the opposite side of the piezoelectric layer and faces the first electrode. In the method, the semiconductor element is formed on the first side ( ) of a silicon wafer ( ). On the same side of this wafer, also the layer of piezoelectric material and the first electrode are formed, after which the surface is covered with the acoustic reflector layer. Subsequently, an adhesive layer ( ) is used to attach the structure thus formed with the acoustic reflector layer to the carrier substrate. Finally, at the location of the filter, silicon is removed from the second side of the wafer, and the comparatively thick acoustic reflector need not be patterned so that underlying features cannot be damaged during etching said reflector layer.