Hierarchical test access port architecture for electronic circuits including embedded core having built-in test access port

Abstract

This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. An internal state in the test access port controller controls the switch state of the programmable switch. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the embedded core circuit under test. The test access port controller can regain control of the first test access port when in snoopy states. At least one of the embedded core circuits includes a test access port controller for similar controlled connection to further embedded core circuits. Test of the entire electronic circuit invloves selection via the programmable switch of an embedded core circuit to test. The embedded programmable switch permits selection of one of the further embedded core circuits. This permits an previous integrated circuit design to be made into an embedded core circuit with no change in testability.