The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2002

Filed:

Oct. 26, 2000
Applicant:
Inventors:

Roy Daron Cideciyan, Rueschlikon, CH;

Jonathan Darrel Coker, Rochester, MN (US);

Evangelos S. Eleftheriou, Zurich, CH;

Richard Leo Galbraith, Rochester, MN (US);

David James Stanek, Rochester, MN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D 1/00 ; H04L 2/706 ; H04L 2/549 ;
U.S. Cl.
CPC ...
H03D 1/00 ; H04L 2/706 ; H04L 2/549 ;
Abstract

Methods and apparatus are provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals using both partial matched filter and matched filter metrics. In the method of the invention, branch metric terms are transformed to shift all time varying terms and some constant terms after an add compare select (ACS) unit. The total number of non-zero constants on trellis branches is minimized. The shifted time varying terms and the shifted constant terms are added directly to state metric terms. The time varying terms are expressed as outputs Z of a partial matched filter or as outputs W of a matched filter. For a given generalized partial response target, the time-invariance property of the Viterbi detector enables identifying the minimum number of non-zero constants on trellis branches without resorting to heuristics. The time-invariance property holds for Viterbi detectors that process multiple samples per trellis-branch, thus allowing implementations at any desired speed.


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