The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2002
Filed:
Dec. 05, 2000
Applicant:
Inventor:
Antonin Rozsypal, Hutisko-Solanec, CZ;
Assignee:
Semiconductor Components Industries LLC, Phoenix, AZ (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/01 ;
U.S. Cl.
CPC ...
H03K 3/01 ;
Abstract
An N-Well bias control circuit ( ) is provided which receives a first voltage (V ) and second voltage (V ) of different magnitudes relating to a battery voltage (V ) and an output voltage (V ) of an up/down DC-DC converter. The bias control circuit provides the voltage of largest magnitude to an output node (V ), which is used to properly bias the N-Well region of a PMOS transistor ( ) to minimize the probability of latch up. The N-Well bias control circuit may also be modified to deliver the minimum of two voltages, V or V , to properly bias the P-Well region of an NMOS transistor.