The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2002

Filed:

Apr. 19, 2000
Applicant:
Inventors:

Dong-yun Lee, Sungnam, KR;

Kee-wook Jung, Sungnam, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/00 ;
U.S. Cl.
CPC ...
H03L 7/00 ;
Abstract

An integrated circuit having a locking circuit and method using the same are provided. The locking circuit includes a time-to-digital converter. The time-to-digital converter includes first and second delay chains, each for delaying one of two input signals at predetermined intervals. The time-to-digital converter also includes first and second phase comparators, each for comparing the delayed signal with the other signal and generating a digital signal. The locking circuit converts the phase difference between a feedback signal and an internal clock signal into a delay control signal group using the time-to-digital converter. The delay control signal group controls the delay time of a mirror delay circuit to rapidly minimize the phase difference between the feedback signal and the internal clock signal.


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