Phase detection circuit

Abstract

The detection circuit comprising: a first D-type flip-flop circuit F/F , to which the data signal D and the clock signal C are input; a first delay circuit DL which delays the clock signal C by a prescribed amount of time, so as to generate a delayed clock signal C ′; a second D-type flip-flop circuit F/F , to which the output signal Q of the first D-type flip-flop circuit F/F and the delayed clock signal C ′ are input; a second delay circuit DL which delays the an output signal Q of the second D-type flip-flop circuit F/F so as to generate a first delayed signal Q ′, a third delay circuit DL which delay the an output signal Q of the first D-type flip-flop circuit F/F so as to generate a second delayed signal Q ′, a fourth delay circuit DL which delays the data signal D so as to generate a delayed data signal D ′, a first AND circuit AND which calculates a logical product of the first delayed signal Q ′ and the second delayed signal Q ′ so as to output a DOWN signal, a second AND circuit AND which calculates a logical product of the second delayed signal Q ′ and the delayed data signal D ′ so as to output an UP signal, and an adder circuit ADD which adds the UP signal and the DOWN signal so as to output a detection signal PDOUT detecting the phase difference between the data signal D and the clock signal C