The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2002

Filed:

Jan. 18, 2000
Applicant:
Inventors:

Kazuo Tomita, Tokyo, JP;

Atsushi Ueno, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/3544 ;
U.S. Cl.
CPC ...
H01L 2/3544 ;
Abstract

A mark structure ( ) consists of a gate oxide film ( ) formed on a semiconductor substrate ( ), a gate wiring layer ( ) formed on the gate oxide film ( ), an insulating film ( ) formed on the gate wiring layer ( ) and a sidewall ( ) formed in contact with side surfaces of the insulating film ( ), the gate wiring layer ( ) and the gate oxide film ( ). An opaque bit line layer ( ) is formed of a polycide consisting of a doped polysilicon layer ( ) and a tungsten silicide layer ( ), extending from on the interlayer insulating film ( ) to on the mark structure ( ). With this structure, a semiconductor device which allows measurement of alignment mark and overlay check mark with high precision in a lithography process, has no structure unnecessary for a mark and suppresses creation of extraneous matter in a process of manufacturing a semiconductor device to prevent deterioration in manufacturing process yield and a method of manufacturing the semiconductor device can be provided.


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