The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2002
Filed:
Jun. 15, 1999
Yuki Miyamoto, Tokyo, JP;
Takeo Ishibashi, Tokyo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A lot determination apparatus and method and a recording medium having the lot determination method recorded thereon, wherein there can be realized a reduction in the number of times wafers are re-subjected to photolithography and prevention of elimination of a chip lot in a subsequent step, by determination of whether or not a chip is conforming through comprehensive determination of results of a plurality of inspections such as an overlay inspection, an etched pattern inspection, and a resist pattern inspection. A determination is made as to whether or not a lot is defective by comprehensive determination of results of a plurality of inspection processes, thereby preventing elimination of the lot as being nonconforming. As a result, specifications for inspections can be relaxed, which in turn enables a reduction in a reprocessing ratio. Further, no short circuit arises between the first and second patterns while determination equations are satisfied, and elimination of a lot in a subsequent process can be prevented. Link check may be carried out not only for each set of measurement points but also on the basis of analysis of results of all the measurement points. Determination equations may be more generalized.