Logic circuit evaluation using sensing latch logic

Abstract

A logic circuit including a logic circuit portion comprised of a dual-rail type logic tree, a synchronization type sensing latch means comprised of a sense amplifier for differentially amplifying results of evaluation of the logic circuit portion in synchronization with a clock, a logic tree disconnection controlling circuit, and a group of switches for disconnection of the logic tree, and a set and reset latch means for holding a logic for one cycle of the synchronization signal, wherein, in an idle stage, the sense amplifier is deactivated, the dual-rail type logic tree unit and sensing latch are connected, and the output terminals of the dual-rail type logic tree are short-circuited, wherein, in the drive stage, the sense amplifier is activated and the output terminals of the dual-rail logic tree are opened, and wherein, in the final determination stage, the sense amplifier is activated and the logic tree and sensing latch unit are disconnected so as to eliminate the glitches to reduce the power consumption and increase the speed.