The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2002

Filed:

Jan. 27, 1999
Applicant:
Inventors:

Akio Tajima, Tokyo, JP;

Yoshihiko Suemura, Tokyo, JP;

Soichiro Araki, Tokyo, JP;

Seigo Takahashi, Tokyo, JP;

Yoshiharu Maeno, Tokyo, JP;

Naoya Henmi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D 3/24 ;
U.S. Cl.
CPC ...
H03D 3/24 ;
Abstract

A bit synchronization circuit operates at high speed range as high as Gb/s or higher and can establish synchronization within 10 bits with rejecting jitter to permit accurate bit synchronization. The bit synchronization circuit thus generates a plurality of clocks having mutually different phases in synchronism with an input reference clock. A phase relationship between a plurality of clocks and an input data to be decided is discriminated by a phase comparator circuit. The clock having optimal phase relationship, namely clock having level transition timing having at a substantially center portion of mutually adjacent level transition timing of the input data, is determined by a phase determination circuit. An decision circuit and selector are provided for deciding input data at the level transition timing of the determined clock.


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