Integrated circuit memory devices with configurable block decoder circuits

Abstract

A memory device includes a memory array and a configurable decoder circuit operatively associated with the memory array and configurable to one of a first state or a second state. In the first state, the configurable decoder circuit is operative, responsive to receipt of an address associated with a portion, e.g., a block, of the memory array, to select the portion while producing a first status signal. In the second state, the configurable decoder circuit is operative, responsive to receipt of an address associated with the portion of the memory array, to prevent selection of the portion while producing a second status signal. The first status signal may indicate, for example, that the portion is valid, while the second status signal may indicate that the portion is invalid. The configurable decoder circuit may include a plurality of configurable block decoder circuits, a respective one of which is coupled to a respective one of a plurality of memory blocks and configurable to one of a first state or a second state. In the first state, the configurable block decoder circuit is operative, responsive to receipt of an address associated with the corresponding memory block, to select the corresponding memory block while producing a first status signal. In the second state, the configurable block decoder circuit is operative, responsive to receipt of an address associated with the corresponding memory block, to prevent selection of the corresponding memory block while producing a second status signal. Related memory device operating methods are also discussed.