The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2002
Filed:
Sep. 08, 2000
Russell C. Smiley, Nepean, CA;
Johan M. Grundlingh, Kinburn, CA;
John J. Ilowski, Nepean, CA;
Robert Leroux, Ottawa, CA;
Nortel Networks Limited, St. Laurent, US;
Abstract
A biasing method and apparatus which provides bias circuits of radio frequency (RF) power transistors with a low reactive impedance at low frequencies to reduce hysteresis related distortion without affecting the transistor input or output impedance or any impedance matching network which may be used. In one embodiment, reduced hysteresis within a lateral diffused metal-oxide semiconductor (LDMOS) transistor is brought about by a drain bias circuit without any impact on the transistor output impedance. By removing the effect of the bias circuit at RF frequencies, the bias circuit can be designed with a low reactive impedance at low frequencies without any material consequences on the transistor output impedance. With a low enough reactive impedance, the hysteresis introduced by the bias circuit is substantially reduced. An auxiliary bias feed external to an RF transistor package is also embodied.