Delay time regulation method and delay time regulation circuit

Abstract

The delay time of a variable delay circuit is set to a desired value by: sequentially applying a plurality of clocks of different frequencies to a variable delay circuit; finding, for each clock, the amount of change in delay time with respect to change in a delay time selection signal, which is a signal for setting the delay time of the variable delay circuit; finding a linear coefficient of the characteristic of the delay time of the variable delay circuit with respect to the delay time selection signal from the difference in the amounts of change with respect to the difference in clock frequencies; finding an amount of offset with respect to the delay time selection signal that pertains to the variable delay circuit from the amounts of change and frequencies of the clocks; and finding the delay time selection signal from the linear coefficient and the difference between the desired delay time and the offset amount.