Fpga lookup table with dual ended writes for ram and shift register modes

Abstract

A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). Each memory circuit includes an inverter circuit connected between the memory cell and the output terminal of the memory circuit. The write decoder includes NOR gates that generate select signals used to address individual memory circuits during write operations. The read decoder includes a multiplexing circuit made up of a series of 2-to-1 multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD.