Control of i.c.'s having different command protocols via common communication lines from a controlling i.c. on a different circuit board

Abstract

A circuit ( ) in which two I.C.'s ( ) are under control of a single microcontroller that issues operating commands to the two I.C.'s via shared communication lines, including a clock line, a serial data line, and a chip enable line. The two I.C.'s use differing communication protocols. For example, a first I.C. uses a common shift register protocol and has a serial data output while a second I.C. uses a C B communication protocol. The chip enable line provides chip enable signal pulses ( ) that are suitable for the chip enable input of the second I.C. ( ). An interface circuit ( ) on the same board that contains the two I.C.'s, interfaces the chip enable line to a strobe input of the first I.C. ( ) to create strobe signal pulses suitable for the protocol of the first I.C. ( ). The interface circuit performs timing and voltage limiting functions. Data enters the second I.C. only after having been clocked through the first I.C.