The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2002
Filed:
Aug. 31, 2000
Keith James Blow, Suffolk, GB;
Alistair James Poustie, Suffolk, GB;
Robert John Manning, Suffolk, GB;
British Telecommunications public limited company, London, GB;
Abstract
A parity determining circuit is used to determine the parity of a binary word. The binary word is represented by a sequence of optical bit slots. Each bit slot defines a respective one of two complementary logical states. The circuit includes: an input pulse stream generator that generates copies of the binary word; a combining device that receives two binary words, offsets one word with respect to the other, and then combines them to form a combination word; and a circuit that applies a copy of the original binary word together with the combination word to the combining device a number of times in succession. This results in a combination word that has a number of bits in the same logical state and that indicates the parity of the binary word.