The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2002
Filed:
Nov. 24, 1999
Leonard R. Rockett, Washington, DC (US);
BAE Systems Information and Electronic Systems Integration Inc., Manassas, VA (US);
Abstract
The present invention provides a single-event upset (SEU) hardened integrated circuit. The integrated circuit includes an SEU hardened asymmetric bi-stable CMOS latch having a first logic state and a second logic state. A supply voltage is operably coupled to the asymmetric bi-stable latch, where upon activation of the supply voltage the asymmetric bi-stable latch is always set to the first logic state. A switch may be provided for changing the latch from the first logic state to the second logic state.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile