Method of manufacturing a semiconductor device

Abstract

In a method of manufacturing a semiconductor device comprising a non-volatile memory element, an active region of a first conductivity type is defined at a surface of a semiconductor body , and a patterned layer is applied, which patterned layer acts as a mask during the formation of a source zone and a drain zone of a second conductivity type in the semiconductor body . Then, a dielectric layer is provided in a thickness which is sufficiently large to cover the patterned layer, which dielectric layer is removed over part of its thickness by means of a material removing treatment until the patterned layer is exposed, which patterned layer is removed, thereby forming a recess in the dielectric layer . In this recess a first insulating layer is applied providing a floating gate dielectric , to which first insulating layer a first conductive layer is applied filling the recess in the dielectric layer , which first conductive layer is shaped into a floating gate by means of masked etching. The floating gate has a substantially flat surface portion extending substantially parallel to the surface of the semiconductor body and sidewall portions extending substantially perpendicularly to the surface of the semiconductor body . In a next step, the floating gate is covered with a second insulating layer providing an inter-gate dielectric , to which second insulating layer a second conductive layer is applied, which is shaped into an overlapping control gate . The control gate is capacitively coupled to the substantially flat surface portion of the floating gate and to at least the sidewall portions of the floating gate situated adjacent to the source zone and the drain zone of the memory element.